1. Field of the Invention
The present invention relates generally to packaging substrates and methods for fabricating the same, and more particularly to a packaging substrate with an embedded semiconductor component and a method for fabricating the same.
2. Description of Related Art
In addition to conventional wire bonding packages, the electronic industry developed, thanks to ever-evolving semiconductor packaging technology, various semiconductor device packages. For example, an IC semiconductor chip can be directly embedded in a packaging substrate and electrically integrated therewith so as to reduce the overall size of the semiconductor device and enhance the electrical function thereof. Such a package type has become a mainstream.
FIGS. 1A to 1D shows a method for fabricating a conventional package structure with an embedded semiconductor component. Referring to FIG. 1A, a first carrier board 10 having a first surface 10a and an opposite second surface 10b is provided, and an cavity 101 penetrating the first surface 10a and the second surface 10b is formed in the first carrier board 10. Further, a second carrier board 11 is provided and the second surface 10b of the first carrier board 10 is coupled to the second carrier board 11. Referring to FIG. 1B, a semiconductor chip 12 is provided, which has an active surface 12a with a plurality of electrode pads 121 thereon and an opposite inactive surface 12b. The inactive surface 12b of the semiconductor chip 12 is fixed, by an adhesion layer 13, in position to the second carrier board 11 exposed from the cavity 101 of the first carrier board 10. Referring to FIG. 1C, a dielectric layer 14 is formed on the first carrier board 10 and the active surface 12a of the semiconductor chip 12 by heat lamination, and also fills the gap between the cavity 101 and the semiconductor chip 12. Referring to FIG. 1D, a plurality of vias 141 are formed in the dielectric layer by laser, and then a plurality of conductive vias 16 and a third wiring layer 15 are respectively formed in the vias 141 and on the dielectric layer 14 to electrically connect to the electrode pads 121 of the semiconductor chip 12.
However, in the above-described prior art, since gap exists between the semiconductor chip 12 and the cavity 101, the semiconductor chip 12 may have a positional deviation e in the cavity 101 caused by such as pressure during the heat lamination of the dielectric layer 14, thereby resulting an alignment deviation between the conductive vias 16 and the electrode pads 121 and even causing failure of the electrical connection between the conductive vias 16 and the electrode pads 121.
Meanwhile, an alignment error may occur during the laser processing for forming the vias 141, thus resulting an alignment deviation between the conductive vias 16 and the electrode pads 121 and even causing failure of the electrical connection therebetween. In addition, the laser processing requires a high cost, has a low speed and is easy to damage the semiconductor chip 12.
Therefore, it is imperative to overcome the above-described drawbacks of the prior art.